Transmitter and receiver, and method of varying a coding rate

ABSTRACT

A data structure of a check matrix for the error correction code is a data structure of a check matrix for an error correction code, in which the error correction code is the LDPC code, and in which the check matrix has a matrix structure in which rows are rearranged for submatrices consisting of a part of columns of the check matrix. Moreover, in the method and device for varying the coding rate of the error correction code, a puncture position that is determined in accordance with a puncture position determination signal is a puncture position with which a number of columns in which two or more 1s are contained in a region of the check matrix that is directly affected by puncturing is minimized.

TECHNICAL FIELD

The present invention relates to a data structure of a check matrix for an error correction code, and a method and device for varying a coding rate of the error correction code.

BACKGROUND ART

An error correction code is a technology used in a communication system, a broadcasting system, a storage apparatus, and the like. More specifically, the error correction code adds redundant bits to digital data for transmission or storage to allow, even when there is an error bit in received data or data read from a storage medium, the error to be corrected. Note, however, that the number of correctable error bits is limited, and the number of correctable error bits is different depending on error correction performance of the error correction code method.

In this field of art, data to be transmitted or stored is referred to as “information bits” , and the redundant bits added to the information bits are referred to as “parity bits” . The parity bits are calculated from the information bits by a calculation method that is different depending on the coding method of the error correction code. In addition, a bit string obtained by combining the information bits and the parity bits is referred to as “codeword”.

An error correction code called “block code” calculates the parity bits from the information bits in units of a predetermined number of bits. In other words, the number of information bits and the number of parity bits in one codeword are predetermined and referred to as “information bit length” and “parity bit length”, respectively. Moreover, the number of bits of the codeword is referred to as “code length”.

In recent years, as the error correction code, a low-density parity-check (LDPC) code has been in wide use. The LDPC code is a block code defined by a sparse parity check matrix (hereinafter referred to as “check matrix”) having a few non-zero elements.

In the specification of the present invention, each matrix element of the check matrix is 0 or 1. Moreover, the number of 1s contained in a column of the check matrix is referred to as “column weight”. Moreover, each column of the check matrix corresponds to each bit forming the codeword. In other words, the number of columns of the check matrix is the code length. Moreover, in a case where the check matrix has full rank, the number of rows of the check matrix is equal to the parity bit length.

Now, a spatially-coupled LDPC code defined by a check matrix as in FIG. 11, for example, has been theoretically analyzed and shown to have high error correction performance (see, for example, Non Patent Literature 1).

In FIG. 11, the outer enclosing rectangle indicates a check matrix for the specially-coupled LDPC code, and the rectangles (check submatrices) therein indicate submatrices for the specially-coupled LDPC code. Matrix elements in parts other than the rectangles indicating the check submatrices are all 0s. Note that, each check submatrix also serves as a check matrix by itself, and a large check matrix formed by diagonally coupling a plurality of the check submatrices as in FIG. 11 is the check matrix for the specially-coupled LDPC code.

The theoretical analysis disclosed in Non Patent Literature 1 evaluates the error correction performance of the specially-coupled LDPC code by using a numerical analysis method called “density evolution” under a condition that the check matrix has the structure as in FIG. 11. As a result of the analysis, the specially-coupled LDPC code has been shown to have high error correction performance approaching the theoretical limit.

CITATION LIST Non Patent Literature

[NPL 1] S. Kudekar, C. Measson, T. J. Richardson, and R. L. Urbanke, “Threshold Saturation on BMS Channels via Spatial Coupling”, CoRR, 2010

SUMMARY OF INVENTION Technical Problem

However, the related art has the following problem.

According to Non Patent Literature 1, the specially-coupled LDPC code is shown to have the high error correction performance, but a specific configuration of the check matrix (that is, specific configuration of each check submatrix) or a configuration method for the check submatrices is not disclosed in Non Patent Literature 1. This is attributed to the nature of the density evolution evaluation method, that is, the fact that the method evaluates the error correction performance without giving any specific configuration of the check submatrices.

In a case where the specially-coupled LDPC code is actually configured and put to practical use, a large difference occurs between error correction performance of the configured specially-coupled LDPC code and the theoretical limit. This is attributed to the specific configuration of the check submatrices, among which an important factor is a closed-loop structure of the check matrix.

For example, as in FIG. 12, a structure obtained by connecting positions of 1s in the check matrix by line segments to allow starting from an arbitrary 1 to follow the line segments back to the original position is referred to as “closed loop”. The number of 1s forming the closed loop is referred to as “length” of the closed loop, and a short closed loop causes degradation in error correction performance of the specially-coupled LDPC code. When the specially-coupled LDPC code is put to practical use, a code length and the like are constrained due to cost requirements such as a circuit scale, and when the specially-coupled LDPC code is configured under such constraints, many short closed loops are generated to degrade the error correction performance.

As described above, in the case where the specially-coupled LDPC code is configured under the practical conditions, there is the problem in that the error correction performance is degraded due to the specific configuration of the check submatrices. One reason is the problem in that the error correction performance is degraded due to the short closed-loop structure of the check matrix.

The present invention has been made in order to solve the above-mentioned problem, and therefore has an object to provide, based on the specially-coupled LDPC code, a data structure of a check matrix for an LDPC code having high error correction performance, and a method and device for varying a coding rate of an error correction code that realize the high error correction performance.

Solution to Problem

In a data structure of a check matrix for an error correction code according to one embodiment of the present invention, the error correction code is an LDPC code, and the check matrix has a matrix structure in which rows are rearranged for submatrices consisting of a part of columns of the check matrix.

Moreover, a coding rate varying device for an error correction code according to one embodiment of the present invention includes: a puncture circuit for removing parity bits in accordance with a puncture position determination signal; and a depuncturing unit for depuncturing the punctured parity bits in accordance with the puncture position determination signal, in which a puncture position that is determined in accordance with the puncture position determination signal is a puncture position with which a number of columns in which two or more 1s are contained in a region of a check matrix that is directly affected by puncturing is minimized.

Moreover, a coding rate varying method for an error correction code according to one embodiment of the present invention includes: a puncture step of removing parity bits in accordance with a puncture position determination signal; and a depuncturing step of depuncturing the punctured parity bits in accordance with the puncture position determination signal, in which a puncture position that is determined in accordance with the puncture position determination signal is a puncture position with which a number of columns in which two or more is are contained in a region of a check matrix that is directly affected by puncturing is minimized.

Advantageous Effects of Invention

According to the data structure of the check matrix for the error correction code according to the one embodiment of the present invention, the error correction code is the LDPC code, and the check matrix has the matrix structure in which the rows are rearranged for the submatrices consisting of the part of columns of the check matrix.

Moreover, the method and device for varying the coding rate of the error correction code according to the one embodiment of the present invention include: the puncture circuit for (puncture step of) removing the parity bits in accordance with the puncture position determination signal; and the depuncturing unit for (depuncturing step of) depuncturing the punctured parity bits in accordance with the puncture position determination signal, in which the puncture position that is determined in accordance with the puncture position determination signal is the puncture position with which the number of columns in which two or more is are contained in the region of the check matrix that is directly affected by the puncturing is minimized.

Therefore, based on the specially-coupled LDPC code, the data structure of the check matrix for the LDPC code having the high error correction performance, and the method and device for varying the coding rate of the error correction code that realizes the high error correction performance may be obtained.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is an explanatory diagram illustrating a cyclic permutation matrix obtained by cyclically shifting a unit matrix.

FIG. 2 is an explanatory diagram illustrating an example of a check matrix for a specially-coupled LDPC code in which check submatrices consist of partitioned matrices of the cyclic permutation matrix.

FIG. 3 is an explanatory diagram illustrating rearrangement of rows for a check matrix for a spatially-coupled QC LDPC code according to a first embodiment of the present invention.

FIG. 4 is an explanatory diagram illustrating the check matrix before the rows of the spatially-coupled QC LDPC code are rearranged.

FIG. 5 is an explanatory diagram illustrating the check matrix after the rows of the spatially-coupled QC LDPC code are rearranged.

FIG. 6 is a flow chart illustrating a procedure of the rearrangement of the rows for the check matrix for the spatially-coupled QC LDPC code according to the first embodiment of the present invention.

FIG. 7 is an explanatory diagram in a case where a coding rate varying device for an error correction code having a puncture function according to a second embodiment of the present invention is applied to a communication system.

FIG. 8 is an explanatory diagram illustrating a degradation in error correction performance in puncturing for a general check matrix for the spatially-coupled QC LDPC code.

FIG. 9 is an explanatory diagram illustrating the error correction performance in the puncturing for the data structure of the check matrix for the LDPC code according to the first embodiment of the present invention.

FIG. 10 is a flow chart illustrating a puncture position determining procedure according to the second embodiment of the present invention.

FIG. 11 is an explanatory diagram illustrating the check matrix for the specially-coupled LDPC code.

FIG. 12 is an explanatory diagram illustrating a problem in the check matrix for the specially-coupled LDPC code.

DESCRIPTION OF EMBODIMENTS

Now, a data structure of a check matrix for an error correction code, and a method and device for varying a coding rate of the error correction code according to preferred embodiments of the present invention are described with reference to the drawings, in which the same or corresponding parts are denoted by the same reference numerals for description.

First Embodiment

Calculating parity bits that enable error correction based on information bits to form a codeword is referred to as “error correction coding”. A calculation procedure for the error correction coding is different for the error correction code method, but in an LDPC code and other such linear block codes, for example, the error correction coding is performed based on the data structure of the check matrix. Now, an example of the error correction coding method is described.

An information bit sequence is represented by d, the check matrix is represented by H, a parity bit sequence to be calculated is represented by p, and the codeword is represented by c, where d, p, and c are vectors, and one vector element corresponds to one bit. As described above, the codeword c consists of the information bit sequence d and the parity bit sequence p, and hence c may be expressed as: c=(d, p).

In a case of a linear block code, c and H have a relationship: cH^(T)=0, where H^(T) represents a transposed matrix of H, and 0 represents a vector in which all elements are 0s. As described above, c=(d, p), and hence (d, p)H^(T)=0 holds. In order to calculate p based on known d and H using this expression, simultaneous linear equations with vector elements of p being variables may be solved. The simultaneous linear equations are equations based on the data structure of the check matrix H, and when solved by Gaussian elimination, for example, the parity bit sequence p may be calculated.

In a first embodiment of the present invention, a description is given of the data structure of the check matrix for the error correction code used in an error correction encoding device and a decoding device.

First, for the LDPC code, terms and definitions used in the description of the present invention are described. FIG. 1 is a matrix obtained by cyclically shifting a unit matrix and is called “cyclic permutation matrix”. In FIG. 1, the term “cyclic shift” refers to an operation of inserting a column, which is displaced to the right of the matrix after the shift in a normal right shift, in the leftmost column of the matrix. In the cyclic shift, the number of columns to be shifted is referred to as “shift amount”.

In a case where the check matrix for the LDPC code is represented by partitioned matrices (also generally referred to as “block matrices”) with cyclic permutation matrices being check submatrices, the LDPC code is referred to as “quasi-cyclic (QC) LDPC code”.

FIG. 2 is an explanatory diagram illustrating an example of the check matrix for the specially-coupled LDPC code in which the check submatrices consist of the partitioned matrices of the cyclic permutation matrix. In FIG. 2, the cyclic permutation matrices illustrated by small rectangles have different shift amounts, but some of the cyclic permutation matrices may have the same shift amounts. The QC LDPC code is relatively simple in terms of the configuration and circuit implementation of the check matrix, and is often used in practice.

When the specially-coupled LDPC code is formed with the check matrices for the QC LDPC code being the check submatrices, a short closed loop, which causes a degradation in error correction performance, often occurs. This short closed loop is the closed loop as illustrated in FIG. 2, for example, and is generated because the shift amount has not been selected appropriately.

However, determining the shift amounts of the cyclic permutation matrices so as not to generate the short closed loop is difficult because the number of combinations is large, and is still a widely studied problem although many practical determining methods have been proposed. Therefore, in the first embodiment of the present invention, a change is made to the spatially-coupled QC LDPC code in terms of positions at which the cyclic permutation matrices are arranged to form the check matrix having a structure in which the closed loop is hardly generated.

Of the short closed loops, ones that especially cause the degradation in error correction performance are closed loops that contain a column having a small column weight. Moreover, as a proportion of columns having small column weights becomes larger, the error correction performance is more likely to be degraded. Such closed loops are likely to generate a structure called “trapping set”, which degrades the error correction performance, and especially affects a degradation in error floor performance.

In order to resolve such short closed loops containing the columns having the small column weights, a structure in which a part of the rows are rearranged for the check matrix for the spatially-coupled QC LDPC code is formed. FIG. 3 is an explanatory diagram illustrating the rearrangement of the rows for the check matrix for the spatially-coupled QC LDPC code according to the first embodiment of the present invention.

In FIG. 3, rows of submatrices consisting of columns having column weights of 3 or more are rearranged. Numbers written to the right of the matrix on the left side of FIG. 3 indicate row block numbers, and the rows are rearranged in units of a row block. Moreover, where each row block is rearranged in the matrix on the right side of FIG. 3 is indicated by the number and the arrow. As used herein, the term “row block” represents a set of rows obtained when the rows of the check matrix are divided with the number of rows corresponding to one cyclic permutation matrix being one unit. The row block numbers are counted in order from the top with the block number at the top of the matrix being 0.

Now, referring to FIGS. 4 and 5, a description is given of how such a rearrangement of the rows resolves the short closed loop containing the columns having the small column weights. FIG. 4 is an explanatory diagram illustrating the check matrix before the rows of the spatially-coupled QC LDPC code are rearranged, and FIG. 5 is an explanatory diagram illustrating the check matrix after the rows of the spatially-coupled QC LDPC code are rearranged.

Note that, in FIG. 4, parts with a column weight of 2 are written so as to be gathered on the right side of the matrix. More specifically, the columns of the check matrix may be written as in FIG. 4 because, even when rearranged, the closed-loop structure and other such characteristics and the error correction performance of the LDPC code do not change. Moreover, in FIG. 5, only columns having column weights of 2 and 3 are written.

The closed loop having a length of 6 illustrated in FIG. 4 consists of one column having the column weight of 3 and two columns having the column weight of 2, and is a big factor that degrades the error correction performance. To the contrary, in the check matrix in which the rows have been rearranged as in FIG. 5, there is no way that the closed loop which has the length of 6 and consists of the one column having the column weight of 3 and the two columns having the column weight of 2 illustrated in FIG. 4 could exist.

In other words, the closed loop which contains only one column having the column weight of 3 and in which the remaining columns are the columns having the column weight of 2 is the closed loop having the structure illustrated in FIG. 5, and in this example, has a length of at least 12. Therefore, the length of the closed loop may be made longer than 6 to resolve the degradation in error correction performance. As described above, arrangements of the cyclic permutation matrices that have been next to each other in FIG. 3 may be separated by the rearrangement of the rows to resolve the short closed loop.

Next, referring to a flow chart of FIG. 6, a description is given of a procedure of the rearrangement of the rows for the check matrix for the spatially-coupled QC LDPC code described above according to the first embodiment of the present invention.

First, the check matrix for the spatially-coupled QC LDPC code is generated (Step S11) . In this case, the check matrix is generated with the use of a well-known conventional method, which includes progressive edge growth, for example.

Next, submatrices consisting of a part of columns of the check matrix generated in Step S11 are subjected to the rearrangement of the rows in accordance with a rule of the following equation (1) (Step S12).

y=ax mod m . . .   (1)

Note that, in the equation (1) , x represents a row block number before the rearrangement, y represents a row block number after the rearrangement, m represents the total number of row blocks, and a represents an integer that is coprime to m.

In this case, the submatrices subjected to the rearrangement of the rows may be submatrices consisting of the above-mentioned columns having the column weights of 3 or more, or may be other submatrices. For example, in a case where there is no column having the column weight of 2 in the check matrix generated in Step S11, submatrices consisting of columns having column weights of 4 or more may be subjected to the rearrangement. Alternatively, submatrices consisting of columns of a value obtained by adding 1 to a value of the smallest column weight in the check matrix or more, or columns of a value obtained by adding a value more than 1 to the value of the smallest column weight or more may be subjected to the rearrangement.

On the other hand, in contrast to the above description, submatrices consisting of columns having column weights of a certain value or less may be subjected to the rearrangement. In any case, the submatrices to be subjected to the rearrangement may be set with the column weight being used as a reference to resolve the closed loop consisting of the columns having the small column weights.

Moreover, without limiting to the column weight used as the reference, submatrices may be selected by another method. For example, the short closed loop is generated in the check matrix for the spatially-coupled QC LDPC code because the cyclic permutation matrices are congested, and there is a possibility that the congestion may be resolved by the rearrangement of the rows to reduce the short closed loops.

Moreover, on the right side of the above-mentioned equation (1) , x and m are determined at a time when the check matrix is generated in Step S11. The remaining a is an integer of 1 or more that is coprime to m. In other words, a is 1 or more and smaller than m, and is a number that is not a divisor of m. In this manner, when x takes a value from 0 to m-1, y also takes a value from 0 to m-1, and the value of y does not overlap for two or more x's.

A specific example of the above-mentioned equation (1) is expressed as the following equation (2). The equation (2) indicates the rearrangement rule used in the example of FIG. 3 described above.

y=3x mod 13 . . .   (2)

Further, an equation that defines the above-mentioned a is expressed as the following equation (3).

$\begin{matrix} \left\lbrack {{Math}.\mspace{14mu} 1} \right\rbrack & \; \\ {a = \left\lfloor \frac{m}{w} \right\rfloor} & (3) \end{matrix}$

Note that, w on the right side of the equation (3) represents the column weight of the submatrices to be subjected to the rearrangement of the rows. Moreover, on the right side of the equation (3), a value obtained by dropping the fractional portion of a value obtained by dividing m by w is written in mathematical symbols.

In this case, a may be defined based on the equation (3) to efficiently resolve the congestion of the cyclic permutation matrices in the check matrix for the spatially-coupled QC LDPC code. More specifically, with a obtained by the equation (3), when the rearrangement of the rows is performed on the submatrices consisting of the columns having the column weights of 3 or more as illustrated in FIG. 5, the closed loop which contains only one column having the column weight of 3 and in which all the other columns contained therein have the column weight of 2 has a length of at least 2a+2.

As described above, the rows of the submatrices of the check matrix for the spatially-coupled QC LDPC code may be rearranged to resolve the short closed loop in the check matrix and hence improve the error correction performance.

Moreover, a communication system, a broadcasting system, and a storage apparatus including the LDPC code having the check matrix to which row rearrangement means is applied may be configured to improve the error correction performance.

Further, in Step S11, in generating the check matrix for the spatially-coupled QC LDPC code, when the density evolution or the like is used to optimize the values of the column weights and a distribution thereof, for example, and hence improve the error correction performance, it is possible to obtain a configuration in which the error correction performance after performing Step S12 is also high.

Further, in the above description, the check matrix for the spatially-coupled QC LDPC code is generated and then the rows are rearranged, but the rearrangement of the rows in Step S12 may be performed before determining the specific values of the shift amount and the like of each cyclic permutation matrix. In this case, a step of determining the shift amount is needed after Step S12.

This eliminates the need to take into consideration a closed loop that is newly generated by the rearrangement of the rows in Step S12, and hence more short closed loops maybe resolved to form the check matrix having the high error correction performance.

Moreover, the check matrix having the configuration in which the submatrices consisting of the columns having the column weight of 2 are arranged in a stair-step shape as illustrated in FIG. 5 may be used to obtain an effect that the parity bits may be calculated with a small amount of operation.

Second Embodiment

In a second embodiment of the present invention, a description is given of a method and device that realize varying a coding rate of the LDPC code having the check matrix of the data structure in the first embodiment described above.

The coding rate is a value expressed by an information bit length divided by a code length. As the coding rate becomes larger, a proportion of the parity bits to all bits to be transmitted by a transmitter and a redundancy become smaller, but the error correction performance becomes lower. To the contrary, as the coding rate becomes smaller, the proportion of the parity bits and the redundancy become larger, but the error correction performance becomes higher. Taking such a relationship into account, it is useful to make the coding rate changeable as needed depending on the system that uses the error correction code and its operating environment.

Now, a related-art method of changing the coding rate includes puncturing of the parity bits. The puncturing removes and does not transmit a part of the calculated parity bits to change the coding rate. FIG. 7 is an explanatory diagram in a case where a coding rate varying device for an error correction code having a puncture function according to the second embodiment of the present invention is applied to a communication system.

In FIG. 7, in the communication system, a transmitter 10 and a receiver 20 are connected to each other via a channel 30. The transmitter 10 includes an LDPC code encoder 11, a puncture circuit 12, and a modulator 13, and the receiver 20 includes a demodulator 21, a depuncturing unit 22, and an LDPC code decoder 23.

On information bits input to the transmitter 10, the LDPC code encoder 11 performs LDPC encoding to output a codeword.

The puncture circuit 12 determines positions in the codeword of parity bits to be punctured in accordance with a puncture position determination signal. Then, the puncture circuit 12 removes the parity bits at the determined positions from the codeword to output the codeword after the puncturing. In this case, the number of parity bits to be punctured may be any number, and may be configured with an arbitrary number.

The modulator 13 converts the codeword after the puncturing into a transmission signal such as a radio wave, light, or an electric signal to be transmitted to the channel 30. The transmitted signal travels the channel 30 to be received by the receiver 20.

The demodulator 21 calculates a log-likelihood ratio (LLR) string based on the received signal and outputs the calculated LLR string. The LLR is a value defined for each bit, and indicates whether the bit is 0 or 1 as well as its likelihood.

For example, when the LLR is a positive value and has a large absolute value, this indicates that the bit is likely to be 0, and when the LLR is a negative value and has a small absolute value, it indicates that the bit is likely to be 1. Moreover, in a case where the LLR is 0, it indicates that there is no information on whether the bit is 0 or 1. Note that, the correspondence of 0 and 1 with the sign may be opposite to the description.

The depuncturing unit 22 performs depuncturing. At this time, the parity bits that have been punctured have not been transmitted from the transmitter 10, and hence the receiver 20 has no information on those bits.

Therefore, the depuncturing unit 22 sets LLRs corresponding to the punctured parity bits to 0s, inserts 0s in appropriate positions of the input LLR string in accordance with the puncture position determination signal, and outputs the LLR string after the depuncturing. In this case, the positions at which 0s are inserted in the LLR string need to be the same as the parity bit positions at which the puncturing has been performed in the puncture circuit 12.

Note that, the LLRs do not always need to be set to 0s. In a case where the information bits, the transmitter, the channel, and the like have characteristics, tendencies, and the like, and a tendency of the parity bits punctured in the puncture circuit 12 is previously known, the LLRs to be set in the depuncturing unit 22 maybe changed accordingly. For example, if the punctured parity bits tend to be 1, the LLRs set in the depuncturing unit 22 may be negative values.

The LDPC code decoder 23 uses the LLR string after the depuncturing to decode the LDPC code, and outputs a bit string as a decoding result.

Next, a description is given of a method of determining the puncture position in the puncture circuit 12 and the depuncturing unit 22. The puncture position affects the error correction performance, and depending on the position, the error correction performance may be degraded significantly. Moreover, depending on the structure of the check matrix, no matter which position is punctured, the significant degradation in error correction performance may occur. In other words, there has been a problem in that the method and device for varying the coding rate of the error correction code having the puncture function degrade the error correction performance.

Therefore, first, for the general check matrix for the spatially-coupled QC LDPC code illustrated in FIG. 8, a cause of degrading the error correction performance in the puncturing is described. In FIG. 8, a case where the puncturing is performed on the bits corresponding to the columns indicated by “puncturing” is described as an example.

In the decoding in the LDPC code, an operation is performed for positions at which the matrix elements in the check matrix are 1s. Therefore, the puncturing has a large effect on the decoding of the punctured columns and the rows in the columns having the matrix elements of 1s. In FIG. 8, the latter is indicated as “region that is directly affected by puncturing”.

More specifically, parts where the matrix elements are 1s inside this region are greatly affected by the puncturing. When many of 1s contained in one column of the check matrix are contained in such a region, the error correction performance for the bits corresponding to the column is degraded. In the specially-coupled LDPC code, the positions of is are relatively congested, and hence when the puncturing is performed, many bits are degraded in terms of the error correction performance.

On the other hand, in the data structure of the check matrix for the LDPC code described in the first embodiment of the present invention, as illustrated in FIG. 9, the positions of 1s in the check matrix are sparse, and hence the puncture position may be determined so as not to generate the column containing many 1s inside the region that is directly affected by the puncturing.

Next, referring to a flow chart of FIG. 10, a description is given of a puncture position determining procedure according to the second embodiment of the present invention.

First, for each parity bit, the region in the check matrix that is directly affected if punctured is calculated (Step S21).

Subsequently, using the region calculated in Step 21, the parity bits to be punctured are determined so that the number of columns in which two or more 1s are contained inside the region that is directly affected by the puncturing is minimized (Step S22) . In other words, the puncture position is determined so that fewer bits are degraded in terms of the error correction performance.

Note that, in Step S22, the columns in which two or more 1s are contained in the region that is affected by the puncturing are minimized, but the number of 1s is not limited to two or more. Further, the determination may be made based not on the number but on the proportion, and the puncture position may be determined so that columns in which more than half of is contained therein are contained in the region that is affected by the puncturing are minimized.

In any case, with a method of determining the puncture position so as to reduce columns in which a plurality of 1s are contained in the region that is directly affected by the puncturing, the effect of the second embodiment of the present invention may be obtained.

The puncture position may be determined as described above to reduce the number of bits that are degraded in terms of the error correction performance, and hence the degradation in error correction performance of the LDPC code by the puncturing may be reduced.

Moreover, for the check matrix having the data structure in the first embodiment described above, the puncture position determining method according to the second embodiment of the present invention described above may be used to further reduce the number of bits that are degraded in terms of the error correction performance and reduce the degradation in error correction performance of the LDPC code due to the puncturing.

Moreover, with the communication system including the puncture position determining method as described above to allow the coding rate to be varied, the degradation in error correction performance of the LDPC code due to the puncturing may be reduced. Further, the communication system may be applied to the LDPC code of the check matrix in the first embodiment described above to further reduce the degradation in error correction performance of the LDPC code due to the puncturing.

Note that, the puncture position may be determined in advance, and information on the determined position may be embedded in a device. Moreover, a plurality of puncture positions including a mode in which the puncturing is not performed and other such modes may be embedded in the device in advance, and control and switching are performed in response to the puncture position determination signal to allow the puncture position to be varied. This allows the puncture function to be equipped in the device in a small circuit scale.

Moreover, in the second embodiment described above, the example of the device in the communication system has been described, but without limiting thereto, the present invention may be applied to the broadcasting system or the storage apparatus to obtain similar effects.

REFERENCE SIGNS LIST

10 transmitter, 11 LDPC code encoder, 12 puncture circuit, 13 modulator, 20 receiver, 21 demodulator, 22 depuncturing unit, 23 LDPC code decoder, 30 channel 

1-7. (canceled)
 8. A transmitter, comprising: an encoder for generating, based on information to be transmitted, a codeword of a low-density parity-check (LDPC) code containing parity bits; and a modulator for modulating the codeword, wherein a check matrix of the LDPC code has a matrix structure in which rows of submatrices consisting of a part of columns of the check matrix are rearranged.
 9. A transmitter according to claim 8, wherein the part of the columns comprises columns each having a column weight, which is a number of 1s contained in the column, of a predetermined value or more.
 10. A transmitter according to claim 9, wherein the predetermined value comprises
 3. 11. A transmitter according to claim 8, further comprising a puncture circuit for removing the parity bits contained in the codeword generated by the encoder in accordance with a determined puncture position, wherein the puncture position comprises such a position as to minimize a number of columns in which two or more 1s are contained in a region that is directly affected by the removal of the parity bits of the check matrix of the LDPC code.
 12. A transmitter according to claim 9, further comprising a puncture circuit for removing the parity bits contained in the codeword generated by the encoder in accordance with a determined puncture position, wherein the puncture position comprises such a position as to minimize a number of columns in which two or more 1s are contained in a region that is directly affected by the removal of the parity bits of the check matrix of the LDPC code.
 13. A transmitter according to claim 10, further comprising a puncture circuit for removing the parity bits contained in the codeword generated by the encoder in accordance with a determined puncture position, wherein the puncture position comprises such a position as to minimize a number of columns in which two or more 1s are contained in a region that is directly affected by the removal of the parity bits of the check matrix of the LDPC code.
 14. A receiver, comprising: a demodulator for demodulating a received signal corresponding to a signal that has been transmitted, the signal being obtained by modulating a codeword being generated by encoding of a low-density parity-check (LDPC) code and containing parity bits; and a decoder for decoding the LDPC code based on the received signal demodulated by the demodulator, wherein a check matrix of the LDPC code has a matrix structure in which rows of submatrices consisting of a part of columns of the check matrix are rearranged.
 15. A receiver according to claim 14, wherein the part of the columns comprises columns each having a column weight, which is a number of 1s contained in the column, of a predetermined value or more.
 16. A receiver according to claim 15, wherein the predetermined value comprises
 3. 17. A receiver according to claim 14, wherein the received signal comprises a signal that is received after having been transmitted, the signal being obtained by removing the parity bits contained in the codeword by puncturing, wherein the receiver further comprises a depuncturing unit for depuncturing, for the demodulated received signal, the parity bits removed by the puncturing in accordance with a determined puncture position, and wherein the puncture position comprises such a position as to minimize a number of columns in which two or more 1s are contained in a region that is directly affected by the removal of the parity bits of the check matrix of the LDPC code.
 18. A receiver according to claim 15, wherein the received signal comprises a signal that is received after having been transmitted, the signal being obtained by removing the parity bits contained in the codeword by puncturing, wherein the receiver further comprises a depuncturing unit for depuncturing, for the demodulated received signal, the parity bits removed by the puncturing in accordance with a determined puncture position, and wherein the puncture position comprises such a position as to minimize a number of columns in which two or more 1s are contained in a region that is directly affected by the removal of the parity bits of the check matrix of the LDPC code.
 19. A receiver according to claim 16, wherein the received signal comprises a signal that is received after having been transmitted, the signal being obtained by removing the parity bits contained in the codeword by puncturing, wherein the receiver further comprises a depuncturing unit for depuncturing, for the demodulated received signal, the parity bits removed by the puncturing in accordance with a determined puncture position, and wherein the puncture position comprises such a position as to minimize a number of columns in which two or more 1s are contained in a region that is directly affected by the removal of the parity bits of the check matrix of the LDPC code.
 20. A method of varying a coding rate, which is to be executed by a transmitter for transmitting a signal encoded into a low-density parity-check (LDPC) code and a receiver for receiving the signal, the method comprising: a puncture step of removing parity bits of a codeword generated by encoding of the LDPC code in accordance with a determined puncture position; and a depuncturing step of depuncturing the parity bits removed in the puncture step in accordance with the puncture position, wherein the puncture position comprises such a position as to minimize a number of columns in which two or more 1s are contained in a region that is directly affected by puncturing of a check matrix of the LDPC code.
 21. A method of varying a coding rate according to claim 20, wherein the check matrix of the LDPC code has a matrix structure in which rows of submatrices consisting of a part of columns of the check matrix are rearranged.
 22. A method of varying a coding rate according to claim 21, wherein the part of the columns comprises columns each having a column weight, which is a number of 1s contained in the column, of a predetermined value or more.
 23. A method of varying a coding rate according to claim 22, wherein the predetermined value comprises
 3. 